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Datasheet File OCR Text:

Da ta S h e et , V 0. 84 , J a n. 2 00 4
H YS64 T 320 00 GU (2 56 M B y t e ) H YS64 T 640 00 GU (5 12 M B y t e ) H YS72 T 640 00 GU (5 12 M B y t e E C C ) H YS64 T 128 02 0GU ( 1 G B y t e ) H YS72 T 128 02 0GU ( 1 G B y t e E C C )
DDR 2 Unb uffe r ed DIMM Mo dul es
M em or y P r od uc t s
Never stop thinking.
HYS64T32000GU HYS64T64000GU, HYS72T64000GU HYS64T128020GU, HYS72T128020GU Preliminary Datasheet Rev. 0.84 (1.04) 1.8 V 240-pin Unbuffered DDR2 SDRAM Modules 256 MByte, 512 MByte & 1 GByte ECC and non-ECC Modules PC2-3200U /-4300U /-5400U
* 240-pin ECC and Non-ECC Unbuffered 8Byte Dual-In-Line DDR2 SDRAM Module for PC, Workstation and Server main memory applications * One rank 32M x 64, 32M x 72, 64M x 64, 64M x 72 and two ranks 128M x 64 and 128M x 72 organization * JEDEC standard Double Data Rate 2 Synchronous DRAMs (DDR2 SDRAM) with a single + 1.8 V ( 0.1 V) power supply * Built with 512Mb DDR2 SDRAMs in 60-ball / 84-ball FBGA chipsize packages * Programmable CAS Latencies (3, 4 & 5), Burst Length (8 & 4) and Burst Type * Auto Refresh (CBR) and Self Refresh * All inputs and outputs SSTL_1.8 compatible * OCD (Off-Chip Driver Impedance Adjustment) and ODT (On-Die Termination) * Serial Presence Detect with E2PROM * Low Profile Modules form factor: 133.35 mm x 30,00 mm (MO-237) * Based on JEDEC standard reference card layouts Raw Card "A", "B" & "C"
* Performance: Speed Grade Indicator Component Speed Grade Module Speed Grade Max. Clock Frequency @ CL = 3 Max. Clock Frequency @ CL = 4 & 5 -5 DDR2-400 PC2-3200 200 200 -3.7 DDR2-533 PC2-4300 200 266 -3 DDR2-667 PC2-5400 200 333 MHz MHz Unit
1.0 Introduction The INFINEON HYS64/72Txxxx0GU module family are low profile Unbuffered DIMM modules with 30,0 mm height based on DDR2 technology. DIMMs are available as non-ECC modules in 32M x 64 (256MB), 64M x 64 (512MB) and 128M x 64 (1024MB) and as ECC-modules in 32M x 72 (256MB), 64M x 72 (512MB) and 128M x 72 (1024MB) organisation and density, intended for mounting into 240 pin connector sockets. The memory array is designed with 512Mb Double Data Rate (DDR2) Synchronous DRAMs for ECC and Non-ECC applications. Decoupling capacitors are mounted on the PCB board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer.
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Rainer.Weidlich@Infineon.com
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HYS 64/72Txx0x0GU Unbuffered DDR2 SDRAM-Modules
1.1 Ordering Information
Type & Partnumber PC2-3200: HYS64T32000GU-5-A HYS64T64000GU-5-A HYS72T64000GU-5-A HYS64T128020GU-5-A HYS72T128020GU-5-A PC2-4300: HYS64T32000GU-3.7-A HYS64T64000GU-3.7-A HYS72T64000GU-3.7-A PC2-4300U-44410-C one rank 256 MB Unb. DIMM PC2-4300U-44410-A one rank 512 MB Unb.DIMM PC2-4300U-44410-A one rank 512 MB Unb.DIMM Non-ECC 512 Mbit (x16) Non-ECC 512 Mbit (x8) ECC 512 Mbit (x8) PC2-3200U-33310-C one rank 256 MB Unb. DIMM PC2-3200U-33310-A one rank 512 MB Unb.DIMM PC2-3200U-33310-A one rank 512 MB Unb.DIMM PC2-3200U-33310-B two ranks 1 GB Unb. DIMM PC2-3200U-33310-B two ranks 1 GB Unb. DIMM Non-ECC 512 Mbit (x16) Non-ECC 512 Mbit (x8) ECC 512 Mbit (x8) Compliance Code Description ECC/ Non-ECC SDRAM Technology
Non-ECC 512 Mbit (x8) ECC 512 Mbit (x8)
HYS64T128020GU-3.7-A PC2-4300U-44410-B two ranks 1 GB Unb. DIMM HYS72T128020GU-3.7-A PC2-4300U-44410-B two ranks 1 GB Unb. DIMM PC2-5400: HYS64T32000GU-3-A HYS64T64000GU-3-A HYS72T64000GU-3-A HYS64T128020GU-3-A HYS72T128020GU-3-A PC2-5400U-44410-C one rank 256 MB Unb. DIMM PC2-5400U-44410-A one rank 512 MB Unb.DIMM PC2-5400U-44410-A one rank 512 MB Unb.DIMM PC2-5400U-44410-B two ranks 1 GB Unb. DIMM PC2-5400U-44410-B two ranks 1 GB Unb. DIMM
Non-ECC 512 Mbit (x8) ECC 512 Mbit (x8)
Non-ECC 512 Mbit (x16) Non-ECC 512 Mbit (x8) ECC 512 Mbit (x8)
Non-ECC 512 Mbit (x8) ECC 512 Mbit (x8)
Notes: 1. All part numbers end with a place code, designating the silicon die revision. Example: HYS 72T64000GU-5-A, indicating Rev. A dies are used for DDR2 SDRAM components. For all INFINEON DDR2 module and component nomenclature see section 8 of this datasheet. 2. The Compliance Code is printed on the module label and describes the speed grade, f.e. "PC2-4300U-44410-C", where 4300U means Unbuffered DIMM modules with 4.26 GB/sec Module Bandwidth and "44410" means CAS latency = 4, trcd latency = 4 and trp latency = 4 using the latest JEDEC SPD Revision 1.0 and produced on the Raw Card "C".
1.2 Address Format
Part Number HYS64T32000GU HYS64T64000GU HYS72T64000GU HYS64T128020GU HYS72T128020GU DIMM Density 256 MB 512 MB 512 MB 1024 MB 1024 MB Module Organization 32M x 64 64M x 64 64M x 72 2 x 64M x 64 2 x 64M x 72 Memory Ranks 1 1 1 2 2 ECC/ Non-ECC Non-ECC Non-ECC ECC Non-ECC ECC # of # of row/bank/ SDRAMs columns bits 4 8 9 16 18 13/2/10 14/2/10 14/2/10 14/2/10 14/2/10 Raw Card C A A B B
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1.3 Components on Modules and RawCard
DIMM Density 256 MB 512 MB 1024 MB DRAM components reference datasheet HYB18T512160AC HYB18T512800AC HYB18T512800AC DRAM Density 512 Mbit 512 Mbit 512 Mbit DRAM Organisation 32Mb x 16 64Mb x 8 64Mb x 8 Raw Card C A B
For a detailed description of all functionalities of the DRAM components on these modules see the referenced component datasheet
1.4 Pin Definition and Function
Pin Name A[13:0] A[9:0] A10/AP BA[1:0] CK[2:0] CK[2:0] RAS CAS WE CS[1:0] CKE[1:0] ODT[1:0] DQ[63:0] Description Row Address Inputs 4) Column Address Inputs Column Address Input for AutoPrecharge SDRAM Bank Selects Clock input
(positive line of differential pair)
Pin Name CB[7:0] DQS[8:0] DQS[8:0] DM[8:0] SCL SDA SA[2:0] VDD VREF VSS
Description DIMM ECC Check Bits 2) SDRAM data strobes 2)
(positive line of differential pair)
SDRAM data strobes 2)
(negative line of differential pair)
SDRAM data mask 2) Serial bus clock Serial bus data line slave address select Power (+ 1.8 V) I/O reference supply Ground EEPROM power supply no connect
Clock input
(negative line of differential pair)
Row Address Strobe Column Address Strobe Read/Write Input Chip Select 3) Clock Enable
3)
VDDSPD NC
Active termination control lines 1) 3) Data Input/Output
1) Active termination only applies to DQ, DQS, DQS and DM signals 2) CB[7:0], DQS8, DQS8 and DM8 are used on ECC modules only and are not connected to components on Non-ECC modules 3) CS1, ODT1 and CKE1 are used on dual rank modules only 4) A13 is not used on memory modules based on x16 organised memory components
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1.5 Pin Configuration
PIN# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Symbol VREF VSS DQ0 DQ1 VSS DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1 DQS1 VSS NC NC VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2 DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DQS3 DQS3 VSS DQ26 DQ27 VSS CB0 / NC 2) PIN# 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 Symbol VSS DQ4 DQ5 VSS DM0 DQS9 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 NC VSS CK1 CK1 VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 NC VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DM3 NC VSS DQ30 DQ31 VSS CB4 / NC 2) CB5 / NC 2) PIN# 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 Symbol A4 VDDQ A2 VDD KEY VSS VSS VDD NC VDD A10/AP BA0 VDDQ WE CAS VDDQ CS1 ODT1 VDDQ VSS DQ32 DQ33 VSS DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DQS5 DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS SA2 PIN# 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 Symbol VDDQ A3 A1 VDD KEY CK0 CK0 VDD A0 VDD BA1 VDDQ RAS CS0 VDDQ ODT0 A13 / NC 3) VDD VSS DQ36 DQ37 VSS DM4 NC VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5 NC VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK2 CK2
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Pin Configuration (cont'd)
PIN# 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Symbol CB1 / NC 2) VSS DQS8 DQS8 VSS CB2 / NC 2) CB3 / NC 2) VSS VDDQ CKE0 VDD NC, (BA2)1) NC VDDQ A11 A7 VDD A5
PIN# 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180
Symbol VSS DM8 NC VSS CB6 / NC 2) CB7 / NC 2) VSS VDDQ CKE1 VDD NC, (A15)1) NC, (A14)1) VDDQ A12 A9 VDD A8 A6
PIN#
Symbol
PIN#
Symbol
102 NC 222 VSS 103 VSS 223 DM6 104 DQS6 224 NC 105 DQS6 225 VSS 106 VSS 226 DQ54 107 DQ50 227 DQ55 108 DQ51 228 VSS 109 VSS 229 DQ60 110 DQ56 230 DQ61 111 DQ57 231 VSS 112 VSS 232 DM7 113 DQS7 233 NC 114 NC 234 VSS 115 VSS 235 DQ62 116 DQ58 236 DQ63 117 DQ59 237 VSS 118 VSS 238 VDDSPD 119 SDA 239 SA0 120 SCL 240 SA1 1) Pins 54, 173 and 174 are not connected on this modules and are reserved for future DIMM module products based on higher density memory components. 2) These pins are the check bit DQ's for ECC unbuffered DIMMs and no-connects for Non-ECC DIMMs 3) Address A13 is not used on memory modules based on x 16 components
1.6 Pin Locations
Front
p in 1 pin 1 21
64 18 4
65 1 85
120 2 40
Backside
240 pin Modules (MO-237)
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HYS 64/72Txx0x0GU Unbuffered DDR2 SDRAM-Modules
1.7 Unbuffered DIMM Input/Output Functional Description
Symbol
CK[2:0], CK[2:0] CKE[1:0] CS[1:0]
Type
Input Input Input Input Input Input Input
Polarity
Function
The system clock inputs. All address and command lines are sampled on the cross point of Cross point the rising edge of CK and the falling edge of CK. Active High Activates the SDRAM clock signals when high and deactivates when low. By deactivating the clocks, CKE low initiates the Power Down Mode or the Self Refresh Mode
Enables the associated SDRAM command decoder when low and disables decoder when Active Low high. When decoder is disabled, new commands are ignored and previous operations continue. This signal provides for external rank selection on systems with multiple ranks. DQ, DQS and Active High When high, termination resistance is enabled for allSet (EMRS). DM pins, assuming this function is enabled in the Extended mode Register Active Low When sampled at the positive edge of the clock, RAS, CAS and WE define the operation to be executed by the SDRAM. DM is an input mask signal for write data. Input data is masked when DM is sampled high Active High coincident with that input data during a write access. DM is samples on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. Selects which internal SDRAM memory bank is activated During Bank Activate command cycle, Address defines the row address. During a Read or Write command cycle, Address defines the column address. In addition to the column address, A10(=AP) is used to invoke Auto-Precharge operation at the end of the burst read or write cycle. If AP is high, Auto Precharge is selected and BA[1:0] defines the bank to be precharged. If AP is low, Auto-Precharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA[1:0] to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA[1:0]. If AP is low, BA[1:0] are used to define which bank to precharge. Data and Check Bit Input /Output pins.
ODT[1:0] RAS, CAS, WE DM[8:0] BA[1:0]
A[13:0]
Input
-
DQ[63:0], CB[7:0]
I/O
-
DQS[8:0], DQS[8:0]
I/O
The data strobes, associated with one data byte, source with data transfer. In Write mode, the data strobe is sourced by the controller and is centered in the data window. In Read mode the data strobe is sources by the DDR2 SDRAM and is sent at the leading edge of the Cross point data window. DQS signals are complements, and timing is relative to the crosspoint of respective DQS and DQS. If the module is to be operated in single ended strobe mode, all DQS signals must be tied on the system board to VSS and DDR2 SDRAM mode registers programmed appropriately. These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range This bidirectional pin is used to transfer data into and out of the SPD EEPROM. A resistor maybe connected from the SDA bus line to VDDSPD on the system level to act as a pull-up. This signal is used to clock data into the SPD EEPROM. A resistor maybe connected from the SCL bus line to VDDSPD on the system planar to act as a pull-up. Isolated power supply for the SDRAM output buffers to provide improved noise immunity. Power and ground for the DDR SDRAM input buffers and core logic. Reference voltage for the SSTL-18 inputs. Serial EEPROM positive power supply, wired to a separated power pin at the connector which supports from 1.7 Volt to 3.6 Volt.
SA[2:0] SDA SCL VDDQ VDD, VSS VREF VDDSPD
Input I/O Input Supply Supply Supply Supply
Note: CS1, ODT1 and CKE1 are used on dual rank modules only.
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2.0 Block Diagrams 2.2 One Rank 32M x 64 (256 MByte) DDR2 SDRAM DIMM Modules (x16 components.) HYS64T32000GU on Raw Card C
CS0 DQS0 DQS0 DM0 LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/ O 12 I/O 13 I/0 14 I/O 15 CS DQS4 DQS4 DM4 LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/ O 12 I/O 13 I/0 14 I/O 15 CS
DQS1 DQS1 DM1
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
D0
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQS5 DQS5 DM5
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
D2
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQS2 DQS2 DM2
DQS3 DQS3 DM3
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/ O 12 I/O 13 I/0 14 I/O 15
CS
DQS6 DQS6 DM6
D1
DQS7 DQS7 DM7
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
CS
D3
VDDSPD
EEPROM Serial PD Clock Input D0 - D3 D0 - D3 D0 - D3 SDA SCL WP A0 A1 A2 CK0, CK0 CK1, CK1 CK2, CK2
Clock Wiring SDRAMs NC 2 SDRAMs 2 SDRAMs
VDD, V DDQ VREF V SS
SA0 SA1 SA2
BA0, BA1 A0 - A12 RAS CAS WE CKE0 ODT0
BA0, BA1 : SDRAMs D0 - D3 A0 - A12 : SDRAMs D0 - D3 RAS : SDRAMs D0 - D3 CAS : SDRAMs D0 - D3 WE CKE ODT : SDRAMs D0 - D3 : SDRAMs D0 - D3 : SDRAMs D0 - D3
DQ-to-I/O wiring may be changed within a byte DQ/DQS/DQS/DM/CKE/S relationships must be maintained as shown DQ/DQS/DQS, adress and control resistors are 22 Ohms +/- 5% BAx, Ax, RAS,CAS, WE resistors are 10 Ohms +/- 5%
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HYS 64/72Txx0x0GU Unbuffered DDR2 SDRAM-Modules
Block Diagrams 2.2 One Rank 64M x 64 / 72 (512 MByte) DDR2 SDRAM DIMM Modules (x8 comp.) HYS64T64000GU / HYS72T64000GU on Raw Card A
CS0 DQS0 DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DQS2 DM2 DM DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQS3 DM3 DM DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8 DQS8 DM8 DM CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS
DQS4 DQS4 DM4 DM DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DQS5 DM5 DM DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DQS7 DM7 DM DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 VDDSPD Serial PD SDA VDD, V DDQ SCL D8 WP A0 A1 A2 VREF V SS Clock Wiring Clock Input CK0, CK0 CK1, CK1 CK2, CK2 SDRAMs 3 SDRAMs 3 SDRAMs 3 SDRAMs D0 - D7, D8 D0 - D7, D8 D0 - D7, D8 CS DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS
D0
D4
D1
D5
D2
D6
D3
D7
EEPROM
SA0 SA1 SA2
D8 for ECC modules only BA0, BA1 A0 - A13 RAS CAS WE CKE0 ODT0 BA0, BA1 : SDRAMs D0 - D7, D8 A0 - A13 : SDRAMs D0 - D7, D8 RAS : SDRAMs D0 - D7, D8 CAS : SDRAMs D0 - D7, D8 WE CKE ODT : SDRAMs D0 - D7, D8 : SDRAMs D0 - D7, D8 : SDRAMs D0 - D7, D8
DQ-to-I/O wiring may be changed within a byte DQ/DQS/DQS/DM/CKE/S relationships must be maintained as shown DQ/DQS/DQS, adress and control resistors are 22 Ohms +/- 5% BAx, Ax, RAS,CAS, WE resistors are 5.1 Ohms +/- 5%
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Block Diagrams 2.3 128M x 64/72 (1GByte) two rank DDR2 SDRAM DIMM Modules (x8 comp.) HYS64T128020GU / HYS72T128020GU on Raw Card B
CS1 CS0 DQS0 DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DQS2 DM2 DM DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQS3 DM3 DM DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8 DQS8 DM8 DM CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS
DQS4 DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DQS5 DM5 DM DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DQS7 DM7 DM DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS
D0
D9
D4
D13
D1
D10
D5
D14
D2
D11
D6
D15
D3
D12
D7
D16
VDDSPD
EEPROM
VDD, V DDQ D17 VREF V SS Serial PD
D0 - D17 D0 - D17 D0 - D17 Clock Wiring SDA
D8
D8 and D17 on ECC modules only BA0, BA1 A0 - A13 RAS CAS WE CKE0 CKE1 ODT0 ODT1 BA0, BA1 : SDRAMs D0 - D17 A0 - A13 : SDRAMs D0 - D17 RAS : SDRAMs D0 - D17 CAS WE CKE CKE ODT ODT : SDRAMs D0 - D17 : SDRAMs D0 - D17 : SDRAMs D0 - D8 : SDRAMs D9 - D17 : SDRAMs D0 - D8 : SDRAMs D9 - D17
SCL
WP A0
A1
A2
Clock Input CK0, CK0 CK1, CK1 CK2, CK2
SDRAMs 6 SDRAMs 6 SDRAMs 6 SDRAMs
SA0 SA1 SA2
DQ-to-I/O wiring may be changed within a byte DQ/DQS/DQS/DM/CKE/S relationships must be maintained as shown DQ/DQS/DQS, adress and control resistors are 22 Ohms +/- 5% BAx, Ax, RAS,CAS, WE resistors are 7.5 Ohms +/- 5%
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3.0 Absolute Maximum Ratings
Parameter Symbol Limit Values min. Voltage on any pins relative to VSS Voltage on VDD relative to VSS Voltage on VDD Q relative to VSS Storage temperature range VIN, VOUT VDD VDDQ TSTG - 0.5 - 1.0 - 0.5 -55 max. 2.3 2.3 2.3 +100
o
Unit
V V
C
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3.1 Operating Temperature Range
Parameter Symbol Limit Values min. DIMM Module Operating Temperature Range (ambient) DRAM Component Case Temperature Range TOPR TCASE 0 0 max. +55 +95
o o
Unit
Notes
C C 1-4
1. DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs. For measurement conditions, please refer to the JEDEC document JESD51-2. 2. Within the DRAM Component Case Temperature range all DRAM specification will be supported. 3. Above 85oC DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 s. 4. Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below 85oC case temperature before initiating self-refresh operation.
3.2 Supply Voltage Levels and DC Operating Conditions
Parameter Symbol min. Device Supply Voltage Output Supply Voltage Input Reference Voltage EEPROM Supply Voltage DC Input Logic High DC Input Logic Low In / Output Leakage Current
1 2 3
Limit Values nom. 1.8 1.8 0.5 x VDDQ - - - max. 1.9 1.9 0.51 x VDDQ 3.6 VDDQ + 0.3 VREF - 0.125 5
Unit
Notes
VDD VDDQ VREF VDDSPD VIH (DC) VIL (DC) IL
1.7 1.7 0.49 x VDDQ 1.7 VREF + 0.125 - 0.30 -5
V V V V V V A
1) 2)
3)
Under all conditions, VDDQ must be less than or equal to VDD Peak to peak AC noise on VREF may not exceed 2% VREF (DC).VREF is also expected to track noise variations in VDDQ. For any pin on the DIMM connector under test input of 0 V VIN VDDQ + 0.3 V.
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4.0 IDD Specifications and Conditions 4.1 256 MByte Non- ECC Module HYS64T32000GU (one rank, four components x16)
256 MByte HYS64T32000GU Symbol Parameter / Condition IDD0 Operating Current IDD1 IDD2P IDD2N IDD2Q
Operating Current Precharge PD Standby Current Precharge Standby Current Precharge Quiet Standby Current
PC2-3200 -5" max. 280 300 16 128 100 52 20 140 340 360 480 24 16 840
PC2-4300 "-3.7" max. 320 360 16 160 120 64 20 160 400 440 520 24 16 880
PC2-5400 "-3" max. 360 420 16 200 140 80 20 200 500 520 520 24 16 960 Unit Note 1 mA mA mA mA mA mA mA mA mA mA mA mA mA mA
1 1 1 1 1 1 1 1 1 1 1 1 1
IDD3P(0) Active PD Standby Current IDD3P(1) LP Active PD Standby Current IDD3N IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
Active Standby Current Operating Current Burst Read Operating Current Burst Write Auto-Refresh Current (tRFCmin.) Auto-Refresh Current (tREFI) Self-Refresh Current Operating Current
Notes: 1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled.
4.2 512 MByte Non-ECC Module HYS64T64000GU (one rank, eight components x8)
512 MByte HYS64T64000GU Symbol Parameter / Condition IDD0 Operating Current IDD1 IDD2P IDD2N IDD2Q
Operating Current Precharge PD Standby Current Precharge Standby Current Precharge Quiet Standby Current
PC2-3200 "-5" max. 440 480 32 256 200 104 40 280 560 600 960 48 32 1040
PC2-4300 "-3.7" max. 520 600 32 320 240 128 40 320 720 760 1040 48 32 1120
PC2-5400 "-3" max. 600 720 32 400 280 160 40 400 840 880 1120 48 32 1280 Unit Note 1 mA mA mA mA mA mA mA mA mA mA mA mA mA mA
1 1 1 1 1 1 1 1 1 1 1 1 1
IDD3P(0) Active PD Standby Current IDD3P(1) LP Active PD Standby Current IDD3N IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
Active Standby Current Operating Current Burst Read Operating Current Burst Write Auto-Refresh Current (tRFCmin.) Auto-Refresh Current (tREFI) Self-Refresh Current Operating Current
Notes: 1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled.
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4.3 512 MByte ECC Module HYS72T64000GU (one rank, nine components x8)
512 MByte HYS72T64000GU Symbol Parameter / Condition IDD0 Operating Current IDD1 IDD2P IDD2N IDD2Q
Operating Current Precharge PD Standby Current Precharge Standby Current Precharge Quiet Standby Current
PC2-3200 "-5" max. 495 540 36 288 225 117 45 315 630 675 1080 54 36 1170
PC2-4300 "-3.7" max. 585 675 36 360 270 144 45 360 810 855 1170 54 36 1260
PC2-5400 "-3" max. 675 810 36 450 315 180 45 450 945 990 1260 54 36 1440 Unit Note 1 mA mA mA mA mA mA mA mA mA mA mA mA mA mA
1 1 1 1 1 1 1 1 1 1 1 1 1
IDD3P(0) Active PD Standby Current IDD3P(1) LP Active PD Standby Current IDD3N IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
Active Standby Current Operating Current Burst Read Operating Current Burst Write Auto-Refresh Current (tRFCmin.) Auto-Refresh Current (tREFI) Self-Refresh Current Operating Current
Notes: 1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled.
4.4 1024 MByte Non-ECC Module HYS64128020GU (two ranks, sixteen components x8)
1024 MByte HYS64T128020GU Symbol Parameter / Condition IDD0 Operating Current IDD1 IDD2P IDD2N IDD2Q
Operating Current Precharge PD Standby Current Precharge Standby Current Precharge Quiet Standby Current
PC2-3200 "-5" max. 472 512 64 512 400 208 80 560 592 632 976 96 64 1072
PC2-4300 "-3.7" max. 552 632 64 640 480 256 80 640 752 792 1060 96 64 1152
PC2-5400 "-3" max. 632 752 64 800 560 320 80 800 872 912 1120 96 64 1312 Unit Note mA 1, 2 mA mA mA mA mA mA mA mA mA mA mA mA mA
1, 2 1, 3 1, 3 1, 3 1, 3 1, 3 1, 3 1, 2 1, 2 1, 2 1, 3 1, 3 1, 2
IDD3P(0) Active PD Standby Current IDD3P(1) LP Active PD Standby Current IDD3N IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
Active Standby Current Operating Current Burst Read Operating Current Burst Write Auto-Refresh Current (tRFCmin.) Auto-Refresh Current (tREFI) Self-Refresh Current Operating Current
Notes: 1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled. 2) The other rank is in IDD2P Precharge Power-Down Standby Current mode 3) Both ranks are in the same IDD current mode
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HYS 64/72Txx0x0GU Unbuffered DDR2 SDRAM-Modules
4.5 1024 MByte ECC Module HYS72T128020GU (two ranks, eighteen components x8)
1024 MByte HYS72T128020GU Symbol Parameter / Condition IDD0 Operating Current IDD1 IDD2P IDD2N IDD2Q
Operating Current Precharge PD Standby Current Precharge Standby Current Precharge Quiet Standby Current
PC2-3200 "-5" max. 531 576 72 576 450 234 90 630 666 711 1116 108 72 1206
PC2-4300 "-3.7" max. 621 711 72 720 540 288 90 720 846 891 1206 108 72 1296
PC2-5400 "-3" max. 711 846 72 900 630 360 90 900 981 1026 1296 108 72 1476 Unit Note mA 1, 2 mA mA mA mA mA mA mA mA mA mA mA mA mA
1, 2 1, 3 1, 3 1, 3 1, 3 1, 3 1, 3 1, 2 1, 2 1, 2 1, 3 1,3 1, 2
IDD3P(0) Active PD Standby Current IDD3P(1) LP Active PD Standby Current IDD3N IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
Active Standby Current Operating Current Burst Read Operating Current Burst Write Auto-Refresh Current (tRFCmin.) Auto-Refresh Current (tREFI) Self-Refresh Current Operating Current
Notes: 1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled. 2) The other rank is in IDD2P Precharge Power-Down Standby Current mode 3) Both ranks are in the same IDD current mode
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4.6 IDD Measurement Conditions
(VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V)
Symbol Parameter/Condition Operating Current - One bank Active - Precharge tCK = tCKmin., tRC = tRCmin., tRAS = tRASmin., CKE is HIGH, CS is high between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. Operating Current - One bank Active - Read - Precharge IOUT = 0 mA, BL = 4, tCK = tCKmin., tRC = tRCmin., tRAS = tRASmin.,tRCD = tRCDmin.,AL = 0, CL = CLmin.; CKE is HIGH, CS is high between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. Precharge Power-Down Current: All banks idle; CKE is LOW; tCK = tCKmin.; Other control and address inputs are STABLE, Data bus inputs are FLOATING. Precharge Standby Current: All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. Precharge Quiet Standby Current: All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and address inputs are STABLE, Data bus inputs are FLOATING. Active Power-Down Current: All banks open; tCK = tCKmin., CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to "0" (Fast Power-down Exit); Active Power-Down Current: All banks open; tCK = tCKmin., CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to "1" (Slow Power-down Exit); Active Standby Current: All banks open; tCK = tCKmin.; tRAS = tRASmax; tRP = tRPmin.,CKE is HIGH; CS is high between valid commands. Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. Operating Current - Burst Read: All banks open; Continuous burst reads; BL = 4;AL = 0, CL = CLmin.; tCK = tCKmin.; tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0mA. Operating Current - Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.; tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; Burst Auto-Refresh Current: tCK = tCKmin., Refresh command every tRFC = tRFCmin. interval, CKE is HIGH, CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. Distributed Auto-Refresh Current: tCK = tCKmin., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. Self-Refresh Current: CKE 0.2V; external clock off, CK and CK at 0V; Other control and address inputs are FLOATING, Data bus inputs are FLOATING. RESET = Low. IDD6 current values are guaranteed up to TCASE of 85oC max. All Bank Interleave Read Current: 1. All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control and address bus inputs are STABLE during DESELECTS. Iout = 0mA.
IDD0 IDD1 IDD2P IDD2N IDD2Q IDD3P(0) IDD3P(1) IDD3N IDD4R IDD4W IDD5B IDD5D IDD6
IDD7
2. Timing pattern: - DDR2 -400-333: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D (12 clocks) - DDR2 -533-444: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D (16 clocks) - DDR2 -667-444: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D (19 clocks) 3. Legend: A = Activate, RA = Read with Auto-Precharge, D=DESELECT
Notes: 1. IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled. 2. Definitions for IDD: LOW is defined as VIN <= VIL(ac)max; HIGH is defined as VIN >= VIH(ac)min. STABLE is defined as inputs are stable at a HIGH or LOW level. FLOATING is defined as inputs are VREF = VDDQ / 2. SWITCHING is defined as: inputs are changing between HIGH and LOW every other clock (once per two cycles) for address and control signals, and inputs changing between HIGH and LOW every other clock (once per cycle) for DQ signals not including mask or strobes. 3. IDD1, IDD4R, and IDD7A current measurements are defined with the outputs disabled (Iout = 0 mA). To achieve this on module level the output buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH. 3. For two rank modules: For all active current measurements the other rank is in Precharge Power-Down Mode IDD2P
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4.6 IDD Measurement Conditions (cont'd)
For testing the IDD parameters, the following timing parameters are used:
-5 PC2-3200 3-3-3 CAS Latency Clock Cycle Time Active to Read or Write delay Active to Active / Auto-Refresh command period Active bank A to Active bank B command delay Active to Precharge Command Precharge Command Period Auto-Refresh to Active / Auto-Refresh command period Average periodic Refresh interval Notes: 1) For modules based on x8 components 2) For modules based on x16 components x8 1) x16 2) CLmin tCKmin tRCDmin tRCmin tRRDmin tRRDmin tRASmin tRPmin tRFCmin tREFI 3 5 15 60 7.5 10 45 15 105 7.8 -3.7 PC2-4300 4-4-4 4 3.75 15 60 7.5 10 45 15 105 7.8 -3 PC2-5400 4-4-4 4 3 12 57 7.5 10 45 12 105 7.8 tCK ns ns ns ns ns ns ns ns s
Unit
Parameter
Symbol
4.7 ODT (On Die Termination) Current
The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1). Depending on address bits A6 & A2 in the EMRS(1) a "week" or "strong" termination can be selected. The current consumption for any terminated input pin, depends on the input pin is in tri-state or driving "0" or "1", as long a ODT is enabled during a given period of time.
ODT current per terminated pin:
EMRS(1) State Enabled ODT current per DQ added IDDQ current for ODT enabled; ODT is HIGH; Data Bus inputs are FLOATING Active ODT current per DQ added IDDQ current for ODT enabled; ODT is HIGH; worst case of Data Bus inputs are STABLE or SWITCHING. A6 = 0, A2 = 1 IODTO A6 = 1, A2 = 0 A6 = 0, A2 = 1 IODTT A6 = 1, A2 = 0 5 6 7.5 mA/DQ 2.5 10 3 12 3.75 15 mA/DQ mA/DQ min. 5 typ. 6 max. 7.5 Unit mA/DQ
note: For power consumption calculations the ODT duty cycle has to be taken into account
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5.0 Electrical Characteristics & AC Timings
5.1 AC Timing Parameter by Speed Grade (Component level data, for reference only) -5 DDR2 -400
Min Max + 600 + 500 0.55 0.55 - 600 - 500 0.45 0.45
Symbol
Parameter
-3.7 DDR2 -533
Min -500 -450 0.45 0.45 Max +500 +450 0.55 0.55
-3 DDR2 -667
Min -450 -400 0.45 0.45 Max +450 +400 0.55 0.55
Unit
tAC tCH tCL tHP tCK tIS tIH tDH tDS tIPW tHZ
DQ output access time from CK/CK
ps ps tCK tCK
tDQSCK DQS output access time from CK/CK
CK, CK high-level width CK, CK low-level width Clock Half Period Clock cycle time CL = 3 CL = 4 & 5
min. (tCL, tCH) 5000 5000 600 600 400 400 0.6 0.35 2*tACmin tACmin 8000 8000 tACmax tACmax tACmax 350 450
min. (tCL, tCH) 5000 3750 600 600 350 350 0.6 0.35 2*tACmin tACmin 8000 8000 tACmax tACmax tACmax 300 400
min. (tCL, tCH) 5000 3000 tbd. tbd. 300 300 0.6 0.35 2*tACmin tACmin 8000 8000 tACmax tACmax tACmax 250 350 WL +0.25 0.60 1.1 0.60 70000 tCK tCK tCK tCK tCK tCK tCK tCK tCK ns ns ns ps ps ps ps ps ps tCK tCK ps ps ps ps ps
Address and control input setup time Address and control input hold time DQ and DM input hold time DQ and DM input setup time Control and Addr. input pulse width (each input)
tDIPW DQ and DM input pulse width (each input)
Data-out high-impedance time from CK/CK
tLZ(DQ) DQ low-impedance from CK / CK tLZ(DQS) DQS low-impedance from CK / CK tDQSQ tQHS tQH
DQS-DQ skew (for DQS & associated DQ signals) Data hold skew factor Data Output hold time from DQS
tHP-tQHS
WL -0.25 0.35 0.2 0.2 2 0.25 0.40 0.9 0.40 45 60 105
WL +0.25 0.60 1.1 0.60 70000 -
tHP-tQHS
WL -0.25 0.35 0.2 0.2 2 0.25 0.40 0.9 0.40 45 60 105
WL +0.25 0.60 1.1 0.60 70000 -
tHP-tQHS
WL -0.25 0.35 0.2 0.2 2 0.35 0.40 0.9 0.40 45 57 105
tDQSS Write command to 1st DQS latching transition tDQSL,H DQS input low (high) pulse width (write cycle) tDSS tDSH
DQS falling edge to CLK setup time (write cycle) DQS falling edge hold time from CLK (write cycle)
tMRD Mode register set command cycle time tWPRE Write preamble tWPST Write postamble tRPRE Read preamble tRPST Read postamble tRAS tRC tRFC
Active to Precharge command Active to Active/Auto-refresh command period Auto-refresh to Active/Auto-refresh command period
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Symbol
Parameter
-5 DDR2 -400
Min Max 12 7.8 3.9
-3.7 DDR2 -533
Min 15 15 7.5 10 2 15 WR+tRP 7.5 7.5 2 6 - AL 2 200 tRFC + 10 3 0 tIS+tCK +tIH Max 12 7.8 3.9
-3 DDR2 -667
Min 12 12 7.5 10 2 15 WR+tRP 7.5 7.5 2 6 - AL 2 200 tRFC + 10 3 0 tIS+tCK +tIH Max 12 7.8 3.9
Unit
tRCD tRP tRRD tCCD tWR tDAL tRTP
Active to Read or Write delay (with and without Auto-Precharge) delay Precharge command period Active bank A to Active bank B command x8 (1k page size) x16 (2k page size)
15 15 7.5 10 2 15
ns ns ns ns tCK ns tCK ns ns tCK tCK tCK tCK ns tCK ns ns s
CAS A to CAS B Command Period Write recovery time
Auto precharge write recovery + precharge time WR+tRP 10 7.5 2 6 - AL 2 200 tRFC + 10 3 0 tIS+tCK +tIH -
tWTR Internal write to read command delay
Internal read to precharge command delay to any valid tXARD Exit power down or Deselect)command (other than NOP power-down tXARDS Exit active lower power) mode to read command (slew exit,
tXP
Exit precharge power-down to any valid command (other than NOP or Deselect)
tXSRD Exit Self-Refresh to read command tXSNR Exit Self-Refresh to non-read command tCKE tOIT tDELAY
CKE minimum high and low pulse width OCD drive mode output delay Minimum time clocks remain ON after CKE asynchronously drops low 0 C - 85 C 85oC - 95oC
o o
Periodic tREFI Average Interval Refresh
1. For details and notes see the relevant INFINEON component datasheet 2. Timing definition and values for tis, tih, tds and tdh may change due to actual JEDEC work. This may also effect the SPD code for these parameters
5.2 ODT AC Electrical Characteristics and Operating Conditions (all speed bins)
Symbol Parameter / Condition min. 2 DDR2-400/533 DDR2-667 tAC(min) tAC(min) tAC(min) + 2 ns 2.5 tAC(min) tAC(min) + 2 ns 3 8 max. 2 tAC(max) + 1 ns tAC(max) + 0.7 ns 2 tCK + tAC(max) + 1 ns 2.5 tAC(max) + 0.6 ns 2.5 tCK + tAC(max) + 1 ns Units
tAOND tAON
ODT turn-on delay ODT turn-on
tCK ns ns tCK ns ns tCK tCK
tAONPD ODT turn-on (Power-Down Modes) tAOFD tAOF tAOFPD tANPD tAXPD
ODT turn-off delay ODT turn-off ODT turn-off delay (Power-Down Modes) ODT to Power Down Mode Entry Latency ODT Power Down Exit Latency
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6.0 Serial Presence Detect Codes for Unbuffered DIMM Modules
Byte# Description Speed Grade SPD Entry Value HYS64T32000GU HYS64T64000GU Hex Value HYS64T128020GU HYS72T128020GU 0E 0A 61 48 02 08 08 1E 80 HYS72T64000GU 80 08 08 0E 0A 60 48 00 05 50 3D 30 60 50 45 02 82 08 08 00 0C 04 38 00 02 00 01 50 3D 30 60 50 45 50 60 3C 30 1E 3C 30 2D 80 60 50 45
0 1 2 3 4 5 6 7 8 9
Number of SPD Bytes Total Bytes in Serial PD Memory Type Number of Row Addresses Number of Column Addresses Number of DIMM Ranks, Package and Height Module Data Width Not used Module Interface Levels Min. Clock Cycle Time at CAS Latency = 5
10
SDRAM Access Time from Clock at CL = 5
11 12 13 14 15 16 17 18 19 20 21 22 23
DIMM Configuration Type Refresh Rate/Type SDRAM Width, Primary Error Checking SDRAM Data Width Reserved Burst Length Supported Number of SDRAM Banks Supported CAS Latencies Not used DIMM Type Information SDRAM Module Attributes SDRAM Device Attributes: General Min. Clock Cycle Time at CAS Latency = 4
24
SDRAM Access Time from Clock for CL = 4
25 26 27 28 29 30 31 32
Minimum Clock Cycle Time at CL = 3 Access Time from Clock at CL = 3 Minimum Row Precharge Time (tRP) Minimum Row Act. to Row Act. Delay (tRRD) Minimum RAS to CAS Delay (tRCD) Minimum RAS Pulse Width (tRAS) Module Density (per rank) Address and Command Setup Time (tIS)
all 128 all 256 all DDR2-SDRAM all 13 / 14 all 10 all 1/2 all x64 / x72 all not used all SSTL_1.8 -5 5 ns -3.7 3.7 ns -3 3 ns -5 0.6 ns -3.7 0.5 ns -3 0.45 ns all non-ECC / ECC all 7.8 s, SR all x16, x8 all na / x8 all all 4&8 all 4 all 5, 4, 3 all not used all unbuffered DIMM all normal DIMM all incl. weak driver -5 5 ns -3.7 3.7 ns -3 3 ns -5 0.6 ns -3.7 0.5 ns -3 0.45 ns all 5 ns all 0.6 ns -5 & -3.7 15 ns -3 12 ns all 10 / 7.5 ns -5 & -3.7 15 ns -3 12 ns all 45 ns -5 -3.7 -3 0.60 ns 0.50 ns 0.45 ns
0D 0A 60 40
0E 0A 60 40
0E 0A 61 40
00 10 00
00 08 00
00 08 00
28
1E
1E
40
80
80
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Byte#
Description
Speed Grade
SPD Entry Value HYS64T32000GU HYS64T64000GU
Hex Value HYS64T128020GU HYS72T128020GU 00 tbd tbd tbd HYS72T64000GU 60 50 45 40 35 30 40 35 30 3C 28 1E 1E 00 00 3C 39 69 80 23 1E 19 2D 28 23 00 00 10 tbd tbd tbd C1 00 XX XX XX XX XX
33
Address and Command Hold Time (tIH)
34
Data Input Setup Time (tDS)
35
Data Input Hold Time (tDH)
-5 -3.7 -3 -5 -3.7 -3 -5 -3.7 -3 all -5 -3.7 & -3 all all -5 & -3.7 -3 all all -5 -3.7 -3 -5 -3.7 -3
0.60 ns 0.50 ns 0.45 ns 0.40 ns 0.35 ns 0.30 ns 0.40 ns 0.35 ns 0.30 ns 15 ns 10 ns 7.5 ns 7.5 ns not used 60 ns 57 ns 105 ns 8 ns 0.35 ns 0.30 ns 0.25 ns 0.45 ns 0.40 ns 0.35 ns not used see note 1 Revision 1.0
36 37 38 39 40 41 42 43 44
Write Recovery Time (tWR) Internal Write to Read Command delay (tWTR) Internal Read to Precharge delay (tRTP) Not used Extension of Byte 41 tRC and Byte 42 tRFC Minimum Core Cycle Time (tRC) Min. Auto Refresh Cycle Time (tRFC) Maximum Clock Cycle Time tck Max. DQS-DQ Skew (tDQSQmax.)
45
Read Data Hold Skew Factor (tQHS)
46 47-61 62 63
Not used Reserved for "Delta Temperature in SPD" SPD Revision Checksum for Bytes 0 - 62
00 tbd tbd tbd
00 tbd tbd tbd
00 tbd tbd tbd
-5 -3.7 -3 INFINEON
64 65-71 72 73-90 91-92 93-94 95-98 99-127
Manufacturers JEDEC ID Code Not used Module Assembly Location Module Part Number Module Revision Code Module Manufacturing Date Module Serial Number Manufacturer's Specific Data
Year/Week Code Serial Number blank blank
FF
128-255 Open for Customer use
Note 1 : Will be used for future SPD Code Revisions. For details of "Delta Temperature in SPD" see JEDEC ballot JC-42.5 Item # 1468.
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HYS 64/72Txx0x0GU Unbuffered DDR2 SDRAM-Modules
7.0 Package Outlines 7.1 Raw Card A Module Package DDR2 Unbuffered DIMM Modules Raw Card A one physical rank, 8 (Non-ECC) or 9 (ECC) components x8
133.35 + 0.15
Front View
Not installed on x64 (Non-ECC) Configuration
2.7 max.
30.0
4.0
pin 1 5,175 63,0
64
65 55,0 5.0
120 5,175
1.27 + 0.1
PCB warpage 0.40
Backside View
pin 121 10.0 184 185 240
17.80
3
3
Detail of Contacts A 0.20 + 0.15 2.50 + 0.20 -
Detail of Contacts B 5.0 0.75R 3.8 typ. 1.5 2.5
0.8 + 0.05
1.0
note: all outline dimensions and tolerances are in accordance with the JEDEC standard (MO-237)
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HYS 64/72Txx0x0GU Unbuffered DDR2 SDRAM-Modules
7.2 Raw Card B Module Package DDR2 Unbuffered DIMM Modules Raw Card B two physical ranks, 16 (Non-ECC) or 18 (ECC) components x8
1 3 3.3 5 + 0.15
4 .0 0 m ax .
Front View
30.0
4 .0
p in 1 5,1 75 6 3,0
64
65 55 ,0 5.0
120 5 ,17 5
1.2 7 + 0.1
PCB warpage 0.40 Not installed on x64 (Non-ECC) Configuration
Backside View
pin 1 21 10.0 1 84 18 5 24 0
17.80
3
3
D e tail of C on tac ts A 0.20 + 0.15 2.50 + 0.20 -
D e ta il o f C o nta cts B 5 .0 0 .75 R 3.8 typ. 1 .5 2 .5
0 .8 1.0
+ 0.05 -
note: all outline dimensions and tolerances are in accordance with the JEDEC standard (MO-237)
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7.3 Raw Card C Module Package DDR2 Registered DIMM Modules Raw Card C one physical rank, 4 components x16 (tbd.)
133.35 + 0.15
2.7 max.
Front View
4.0 30.0
pin 1 5,175 63,0
64
65 55,0 5.0
120 5,175
1.27 + 0.1
PCB warpage 0.40
Backside View
pin 121 10.0 184 185 240
17.80
3
3
Detail of Contacts A 0.20 + 0.15 2.50 + 0.20 -
Detail of Contacts B 5.0 0.75R 3.8 typ. 1.5 2.5
0.8 + 0.05
1.0
note: all outline dimensions and tolerances are in accordance with the JEDEC standard (MO-237)
INFINEON Technologies
23
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HYS 64/72Txx0x0GU Unbuffered DDR2 SDRAM-Modules
8.0 Nomenclature (Modules & Components)
8.1 DDR2 DIMM Modules
1 Example:
1 2 3
INFINEON Prefix Module Data Width DRAM Technology
2 72
3 T
4 128
5 0
6 2
7 8 9
7 0
8 G
9 U
10 -5
11 -A
0 = standard G = standard modules H = "green" modules R = Registered DIMMs U = Unbuffered DIMMs DL = Small Outline DIMMs) -5 = PC2-3200 (DDR2-400) -3.7 = PC2-4300 (DDR2-533) -3 = PC2-5400 (DDR2-667) A = 1st Generation B = 2nd Generation C = 3rd Generation
HYS
HYS for DIMM Modules 64 = Non-ECC Modules 72 = ECC Modules T = DDR2 64 = 64 Mb 128 = 128 Mb 256 = 256 Mb 0 = first generation 0 = One Rank 2 = Two Ranks
Product Variations Package Module Type
4
Memory Density per I/O
10 Speed Grade
5
Raw Card Generation Number of Memory Ranks
11 Die Revision
6
Multiplying "Memory Density per I/O" with "Module Data Width" and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall module memory density in MBytes.
8.2 DDR2 Memory Components
1 Example: HYB
2 18
3 T
4 512
5 80
6 0
7 A
8 C
9 -5
1 2
INFINEON Component Prefix Power Supply Voltage
HYB for DRAM Components 18 = 1.8 V Power Supply
6 7
Product Variations Die Revision
0 = standard A = 1st Generation B = 2nd Generation C = 3rd Generation C = BGA package F = BGA package (lead and halogen free) -5 =...DDR2-400 -3.7 =.DDR2-533 -3 =...DDR2-667
3
DRAM Technology
T = DDR2 256 = 256 Mb 512 = 512 Mb 1G = 1024Mb 40 = x4, 4 data in/outputs 80 = x8, 8 data in/outputs 16 = x16, 16 data in/outputs
8 9
Package Type
4
Memory Density
Speed Grade
5
Memory Organisation
INFINEON Technologies
24
1.04

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